NEC Computer Hardware V850 SF1 User Manual

User’s Manual  
IE-703079-MC-EM1  
In-circuit Emulator Option Board  
Target device  
V850/SF1™  
Document No. U15447EJ1V0UM00 (1st edition)  
Date Published September 2001 N CP(K)  
2001  
©
Printed in Japan  
 
V850 Family and V850/SF1 are trademarks of NEC Corporation.  
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States  
and/or other countries.  
PC/AT is a trademark of International Business Machines Corporation.  
Ethernet is a trademark of Xerox Corporation.  
The information in this document is current as of May, 2001. The information is subject to change  
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data  
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products  
and/or types are available in every country. Please check with an NEC sales representative for  
availability and additional information.  
No part of this document may be copied or reproduced in any form or by any means without prior  
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NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of  
third parties by or arising from the use of NEC semiconductor products listed in this document or any other  
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any  
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Descriptions of circuits, software and other related information in this document are provided for illustrative  
purposes in semiconductor product operation and application examples. The incorporation of these  
circuits, software and information in the design of customer's equipment shall be done under the full  
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's  
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(Note)  
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.  
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for  
NEC (as defined above).  
M8E 00. 4  
User’s Manual U15447EJ1V0UM  
3
 
Regional Information  
Some information contained in this document may vary from country to country. Before using any NEC  
product in your application, pIease contact the NEC office in your country to obtain a list of authorized  
representatives and distributors. They will verify:  
Device availability  
Ordering information  
Product release schedule  
Availability of related technical literature  
Development environment specifications (for example, specifications for third-party tools and  
components, host computers, power plugs, AC supply voltages, and so forth)  
Network requirements  
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary  
from country to country.  
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Tel: 408-588-6000  
800-366-9782  
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.  
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Fax: 040-2444580  
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Seoul, Korea  
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Fax: 01-3067-5899  
Fax: 0211-65 03 490  
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Electron Devices Division  
Guarulhos-SP, Brasil  
Tel: 11-6462-6810  
Fax: 11-6462-6829  
J01.2  
Users Manual U15447EJ1V0UM  
4
 
INTRODUCTION  
Target Readers  
Purpose  
This manual is intended for users who design and develop application systems using  
the V850/SF1™.  
The purpose of this manual is to describe the proper operation of the IE-703079-MC-  
EM1 and its basic specifications.  
Organization  
This manual is divided into the following parts.  
Overview  
Names and functions of components  
Cautions  
How to Read This Manual  
It is assumed that the reader of this manual has general knowledge in the fields of  
electrical engineering, logic circuits, and microcontrollers.  
The IE-703079-MC-EM1 is used connected to the IE-703002-MC in-circuit emulator.  
This manual explains the basic setup procedure and switch settings of the IE-  
703002-MC when it is connected to the IE-703079-MC-EM1. For the names and  
functions of parts, and the connection of elements, refer to the IE-703002-MC User’s  
Manual (U11595E).  
To learn about the basic specifications and operation methods  
Read this manual in the order of the CONTENTS.  
To learn the operation methods and command functions, etc., of the IE-703002-MC  
and IE-703079-MC-EM1  
Read the user’s manual of the debugger (sold separately) that is used.  
Conventions  
Note:  
Footnote for item marked with Note in the text  
Caution:  
Remark:  
Information requiring particular attention  
Supplementary information  
Numeral representation: Binary  
Decimal  
xxxx or xxxxB  
xxxx  
Hexadecimal  
xxxxH  
Prefix indicating the power of 2 (address space, memory capacity):  
K (kilo):  
210 = 1024  
220 = 10242  
M (mega):  
Terminology  
The meanings of terms used in this manual are listed below.  
Target device  
Target system  
The device that is targeted for emulation.  
The system (user-built system) that is targeted for debugging. This  
includes the target program and user-configured hardware.  
5
User’s Manual U15447EJ1V0UM  
 
Related Documents  
When using this manual, refer to the following manuals.  
The related documents indicated in this publication may include preliminary versions.  
However, preliminary versions are not marked as such.  
{ Documents related to development tools (user’s manuals)  
Document Name  
Document  
Number  
IE-703002-MC In-circuit emulator  
IE-703079-MC-EM1 In-circuit emulator option board  
U11595E  
U15447E  
U15024E  
U15025E  
U15026E  
U15027E  
CA850 C Compiler package Ver. 2.40  
or later  
Operation  
C Language  
Project Manager  
Assembly Language  
Operation  
ID850 Integrated debugger Ver.2.40  
WindowsTM based  
To be  
prepared  
SM850 System simulator Ver.2.40  
Windows based  
Operation  
To be  
prepared  
SM850 System simulator Ver.2.00 or  
later  
External Part User Open  
Interface Specifications  
U14873E  
RX850 Real-time OS Ver.3.13 or later  
RX850 Pro Real-time OS Ver.3.13  
Basics  
U13430E  
U13410E  
U13431E  
U13773E  
U13774E  
U13772E  
U13737E  
U13916E  
U14410E  
Installation  
Technical  
Basics  
Installation  
Technical  
RD850 Task debugger Ver.3.01  
RD850 Pro Task debugger Ver.3.01  
AZ850 System performance analyzer Ver.3.0  
6
User’s Manual U15447EJ1V0UM  
 
CONTENTS  
CHAPTER 1 OVERVIEW.........................................................................................................................10  
1.1  
1.2  
1.3  
1.4  
1.5  
1.6  
Hardware Configuration...............................................................................................................................10  
Features (When Connected to IE-703002-MC) ...........................................................................................11  
Function Specifications (When Connected to IE-703002-MC)..................................................................11  
System Configuration ..................................................................................................................................12  
Contents in Carton .......................................................................................................................................13  
Connection Between IE-703002-MC and IE-703079-MC-EM1....................................................................15  
CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS ...............................................................18  
2.1  
2.2  
Component Names and Functions of IE-703079-MC-EM1 ........................................................................18  
Clock Settings...............................................................................................................................................20  
2.2.1  
2.2.2  
Main system clock setting.................................................................................................................20  
Subsystem clock setting...................................................................................................................21  
2.3  
2.4  
Illegal Access Detection ROM Setting ........................................................................................................22  
CPU Operation Voltage Range Switching Setting .....................................................................................22  
CHAPTER 3 FACTORY SETTINGS........................................................................................................23  
CHAPTER 4 CAUTIONS .........................................................................................................................24  
4.1  
4.2  
4.3  
4.4  
4.5  
VDD0 and PORTVDD of Target System ..........................................................................................................24  
NMI Signal .....................................................................................................................................................25  
VPP Signal ......................................................................................................................................................25  
NMI Signal Mask Function ...........................................................................................................................25  
Bus Interface Pin ..........................................................................................................................................26  
CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICE AND TARGET INTERFACE CIRCUIT....28  
APPENDIX PACKAGE DRAWINGS ........................................................................................................34  
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User’s Manual U15447EJ1V0UM  
 
LIST OF FIGURES  
Figure No.  
Title  
Page  
1-1  
1-2  
1-3  
1-4  
System Configuration ........................................................................................................................................12  
Contents in Carton.............................................................................................................................................13  
Accessories .......................................................................................................................................................14  
Connection Between IE-703002-MC and IE-703079-MC-EM1..........................................................................16  
2-1  
IE-703079-MC-EM1...........................................................................................................................................18  
4-1  
4-2  
Schematic Diagram of Power Supply Acquisition..............................................................................................24  
NMI Signal Flow Path ........................................................................................................................................25  
5-1  
Equivalent Circuit of Emulation Circuit...............................................................................................................29  
8
User’s Manual U15447EJ1V0UM  
 
LIST OF TABLES  
Table No.  
Title  
Page  
2-1  
2-2  
2-3  
2-4  
Main System Clock Setting................................................................................................................................20  
Subsystem Clock Setting...................................................................................................................................21  
JP1 Setting in IE-703002-MC............................................................................................................................22  
JP3 and JP4 Setting in IE-703002-MC..............................................................................................................22  
4-1  
Bus Interface Pin Operation List........................................................................................................................26  
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User’s Manual U15447EJ1V0UM  
 
CHAPTER 1 OVERVIEW  
The IE-703079-MC-EM1 is an option board for the IE-703002-MC in-circuit emulator. By connecting the IE-  
703079-MC-EM1 and IE-703002-MC, hardware and software can be debugged efficiently in system development  
using the V850/SF1.  
In this manual, the basic setup procedure and switch settings of the IE-703002-MC when connecting the IE-  
703079-MC-EM1 are described. For the names and functions of the parts of the IE-703002-MC, and for the  
connection of elements, refer to the IE-703002-MC User’s Manual (U11595E).  
1.1 Hardware Configuration  
Optional hardware  
In-circuit emulator (IE-703002-MC)  
Option board  
By adding this board, the IE-703002-MC can be used as in-circuit  
emulator for V850/SF1.  
(IE-703079-MC-EM1)  
Optional hardware  
Extension probe  
General-purpose extension probe made by TOKYO ELETECH  
CORPORATION  
SWEX-100SD (for GC/GF package)Note 1  
GF-N17DT (for GF package)Note 1  
PC interface board  
IE-70000-PC-IF-CNote 2  
IE-70000-98-IF-CNote 2  
IE-70000-PCI-IF-A  
IE-70000-CD-IF-A  
This board is used to connect the IE-703002-MC to a personal  
computer. This board is inserted in the expansion slot of the  
personal computer.  
IE-70000-PC-IF-C: for IBM PC/ATTM compatible ISA bus  
IE-70000-98-IF-C: for PC-9800 series C bus  
IE-70000-PCI-IF-A: for PCI bus  
IE-70000-CD-IF-A: for PCMCIA socket  
Network module  
This module is used when a workstation controls the IE-703002-MC  
via Ethernet™.  
(IE-70000-MC-SV3)  
Power adapter  
AC adapter for in-circuit emulator made by NEC Corporation.  
(IE-70000-MC-PS-B)  
Notes 1. For further information, contact Daimaru Kogyo Co., Ltd.  
Tokyo Electronics Department (TEL +81-3-3820-7112)  
Osaka Electronics Department (TEL +81-6-6244-6672)  
2. Cannot be used for PC98-NX series  
10  
User’s Manual U15447EJ1V0UM  
 
CHAPTER 1 OVERVIEW  
1.2 Features (When Connected to IE-703002-MC)  
{
{
{
{
Maximum operating frequency: 16 MHz (at 5.0 V operation)  
Extremely lightweight and compact  
Higher equivalence with target device can be achieved by omitting buffer between signal cables.  
The following pins can be masked.  
RESET, NMI, WAIT, HLDRQ  
{
{
Two methods of connection to target system:  
• Pod tip direct connection (For information on the pod, refer to the IE-703002-MC User’s Manual (U11595E))  
• Attach an extension probe (sold separately) to the pod tip for connection  
The dimensions of the IE-703079-MC-EM1 are as follows.  
Parameter  
Power consumption (Max. value at 5.0 V supply voltage)  
Value  
2.5 W (at 16 MHz operation frequency)Note  
External dimensions  
(Refer to APPENDIX PACKAGE  
DRAWINGS)  
Height  
Length  
Width  
50 mm  
130 mm  
252 mm  
300 g  
Weight  
Note 12.5 W when IE-703002-MC connected to IE-703079-MC-EM1  
1.3 Function Specifications (When Connected to IE-703002-MC)  
Parameter  
Specification  
Emulation memory capacity  
Internal ROM  
256 KB  
2 MB  
External  
memory  
In ROMless mode  
When using iROM  
1 MB  
Coverage memory capacity for  
execution/pass detection  
Internal ROM  
256 KB  
2 MB  
External  
memory  
In ROMless mode  
When using iROM  
1 MB  
Coverage memory capacity for  
memory access detection  
External memory  
1 MB  
Coverage memory capacity for  
branching entry number counting  
Internal ROM  
256 KB  
2 MB  
External  
memory  
In ROMless mode  
When using iROM  
1 MB  
Caution  
Some of the functions may not be supported, depending on the debugger used.  
11  
User’s Manual U15447EJ1V0UM  
 
CHAPTER 1 OVERVIEW  
1.4 System Configuration  
The system configuration when connecting the IE-703002-MC to the IE-703079-MC-EM1 and a personal computer  
(PC-9800 series or PC/AT (or compatibles)) is shown below.  
Figure 1-1. System Configuration  
<13>  
<5>  
<6>  
<7>  
[Magnified drawing: example of use of  
connector for target connection]  
<12>  
<14>  
<8>  
<4>  
<10>  
Target  
system  
<11>  
<9>  
<3>  
<10>  
<11>  
<1>, <2>  
Target system  
Remark  
<1> Personal computer (PC-9800 series or PC/AT or compatibles)  
<2> Debugger (ID850: sold separately)  
<3> PC interface board  
(IE-70000-98-IF-C/IE-70000-PC-IF-C, IE-70000-PCI-IF-A/IE-70000-CD-IF-A: sold separately)  
<4> PC interface cable (included with IE-703002-MC)  
<5> In-circuit emulator (IE-703002-MC: sold separately)  
<6> In-circuit emulator option board (IE-703079-MC-EM1: this product)  
<7> External logic probe (included with IE-703002-MC)  
<8> Socket for target connection (YQSOCKET100SDN: sold separately)  
<9> Extension probe (for GC package: SWEX-100SD, for GF package: SWEX-100SD/GF-N17DT)  
<10> Connector for emulator connection (YQPACK100SD: included)  
<11> Connector for target connection (NQPACK100SD: included)  
<12> Power adapter (IE-70000-MC-PS-B: sold separately)  
<13> AC100V power cable (sold separately: included with IE-70000-MC-PS-B)  
<14> AC220V power cable (sold separately: included with IE-70000-MC-PS-B)  
12  
User’s Manual U15447EJ1V0UM  
 
CHAPTER 1 OVERVIEW  
1.5 Contents in Carton  
The carton of the IE-703079-MC-EM1 contains a main unit, guarantee card, packing list, and accessory bag.  
Make sure that the accessory bag contains this manual and the connector accessories. If there are missing or  
damaged items, please contact an NEC sales representative or an NEC distributor.  
Figure 1-2. Contents in Carton  
<1> IE-703079-MC-EM1  
<4> Packing list  
<3> Guarantee card  
<2> Accessory bag  
<1> IE-703079-MC-EM1 × 1  
<2> Accessory bag × 1  
<3> Guarantee card × 1  
<4> Packing list × 1  
13  
Users Manual U15447EJ1V0UM  
 
CHAPTER 1 OVERVIEW  
Check that the accessory bag contains this manual, an accessory list (× 1), and the following accessories.  
(a) Spacers × 4  
(b) Screws/washers × 4 sets  
(including screws and washer × 4)  
Figure 1-3. Accessories  
(a) Spacers  
(b) Screws/washers  
14  
Users Manual U15447EJ1V0UM  
 
CHAPTER 1 OVERVIEW  
1.6 Connection Between IE-703002-MC and IE-703079-MC-EM1  
The procedure for connecting the IE-703002-MC and IE-703079-MC-EM1 is described below.  
Caution  
Connect carefully so as not to break or bend connector pins.  
<1> Remove the pod cover (upper and lower) of the IE-703002-MC.  
<2> Set the PGA socket lever of the IE-703079-MC-EM1 to the OPEN position as shown in Figure 1-4 (b).  
<3> Connect the IE-703079-MC-EM1 to the PGA socket at the back of the IE-703002-MC pod (refer to Figure 1-4  
(c)). When connecting, position the IE-703002-MC and IE-703079-MC-EM1 so that they are horizontal.  
<4> Set the PGA socket lever of the IE-703079-MC-EM1 to the CLOSE position as shown in Figure 1-4 (b).  
<5> Set the IE-703002-MC pod jumpers (JP1 to JP3).  
The factory settings of JP2 are pins 1 and 2 shorted.  
<6> Place the supplied spacers in the four corner holes of the IE-703079-MC-EM1. Fix the spacers with the  
supplied screws.  
<7> Fix the IE-703002-MC pod cover (upper) end with nylon rivets.  
15  
User’s Manual U15447EJ1V0UM  
 
CHAPTER 1 OVERVIEW  
Figure 1-4. Connection Between IE-703002-MC and IE-703079-MC-EM1 (1/2)  
(a) Overview  
Screw  
Upper cover  
Washer  
IE-703079-MC-EM1  
Nylon rivets  
IE-703002-MC  
Spacer  
(b) PGA socket lever of IE-703079-MC-EM1  
CLOSE  
OPEN  
16  
Users Manual U15447EJ1V0UM  
 
CHAPTER 1 OVERVIEW  
Figure 1-4. Connection Between IE-703002-MC and IE-703079-MC-EM1 (2/2)  
(c) Connecting part (IE-703079-MC-EM1)  
Pin A1 position  
: Insertion guide  
: IE-703002-MC insertion area  
17  
Users Manual U15447EJ1V0UM  
 
CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS  
This chapter describes the names, functions, and switch settings of components in the IE-703079-MC-EM1. For  
the details of the pod, jumper, and switch positions, etc., refer to the IE-703002-MC User’s Manual (U11595E).  
2.1 Component Names and Functions of IE-703079-MC-EM1  
Figure 2-1. IE-703079-MC-EM1  
(a) Top view  
(b) Bottom view  
Direction of pin 1 of connector  
for target connection  
Direction of pin 1 of connector  
for target connection  
Connector for target connection  
CP15  
CP1  
V850/SF1  
I/O chip  
FPGA  
V850/SF1  
I/O chip  
JP2  
Connector for  
IE-703002-MC connection  
CP2  
CP13  
18  
User’s Manual U15447EJ1V0UM  
 
CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS  
(1) TEST pins (CP1, CP2, CP13, CP15)  
These are pins used for testing the analog signals of the standalone emulator.  
CP1: GND  
CP2: GND  
CP13: GND  
CP15: GND  
(2) JP1  
This is a pin board for supplying the main system clock.  
(3) JP2  
This is the switch jumper for the main system clock supply source. Use and retain the factory settings (pins 1  
and 2 shorted).  
(4) JP3  
This is a pin board for supplying the subsystem clock (for details, refer to 2.2 Clock Settings).  
(5) Connector for IE-703002-MC connection  
This is a connector for connecting with the IE-703002-MC.  
(6) Connector for target connection  
This is a connector for connecting with the target system or the extension probe.  
19  
Users Manual U15447EJ1V0UM  
 
CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS  
2.2 Clock Settings  
This section describes the clock settings.  
For the position of the JP1 and JP2 in the IE-703079-MC-EM1, refer to Figure 2-1.  
For the jumper switch position in the IE-703002-MC, refer to the IE-703002-MC User’s Manual (U11595E).  
2.2.1 Main system clock setting  
Table 2-1. Main System Clock Setting  
Emulator Use  
Environment  
Clock Supply  
Method  
IE-703079-MC-EM1 Setting  
IE-703002-MC Setting  
SW2 JP2  
JP1  
JP2  
2
SW1  
ON  
When using  
emulator as  
Internal clock  
OFF  
1
1
3
3
7
8
1
2
standalone unit  
1
1
7
7
When using  
emulator with  
target system  
Internal clock  
2
Caution Emulation cannot be performed by inputting a clock from the target board.  
The specifications of JP1 are as follows.  
V850/SF1  
I/O  
chip  
X1  
X2  
1 M  
GND  
GND  
1
7
10 pF  
16 MHz  
10 pF  
20  
Users Manual U15447EJ1V0UM  
 
CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS  
2.2.2 Subsystem clock setting  
Table 2-2. Subsystem Clock Setting  
Emulator Use  
Environment  
Clock Supply Method  
IE-703079-MC-EM1 Setting  
JP3  
When using emulator as  
standalone unit  
Internal clockNote 1  
Internal clockNote 1  
Oscillator mounted (a 32.768 kHz oscillator is mounted when  
shipped)Note 2  
When using emulator with  
target system  
Oscillator mounted (a 32.768 kHz oscillator is mounted when  
shipped)Note 2  
Notes 1. The internal clock does not support the clock input by an oscillator.  
2. To use a subsystem clock frequency other than 32.768 kHz, remove the resonator on JP3 and mount  
any oscillator.  
The specifications of JP3 are as follows.  
V850/SF1  
I/O chip  
XT1  
XT2  
XT1  
GND  
GND  
7
1
27 pF  
32.768 kHz  
27 pF  
Caution Emulation cannot be performed by inputting a clock from the target board.  
21  
Users Manual U15447EJ1V0UM  
 
CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS  
2.3 Illegal Access Detection ROM Setting  
If using the IE-703002-MC for an in-circuit emulator for the V850/SF1 by connecting the IE-703079-MC-EM1, set  
JP1 of the IE-703002-MC as follows.  
Table 2-3. JP1 Setting in IE-703002-MC  
JP1  
Description  
OpenNote  
Illegal access detection ROM (mounted on IE-703079-MC-EM1) for V850/SF1 is  
used.  
JP1  
Note When JP1 is set open, keep the removed jumper contact attached to one pin  
as shown in the drawing on the right.  
Jumper  
contact  
2.4 CPU Operation Voltage Range Switching Setting  
If using the IE-703002-MC for an in-circuit emulator for the V850/SF1 by connecting the IE-703079-MC-EM1, set  
JP3 and JP4 of the IE-703002-MC as follows.  
Table 2-4. JP3 and JP4 Setting in IE-703002-MC  
JP3, JP4  
Description  
JP3  
JP4  
The operation voltage range of the IE-703002-MC is 3.0 to 5.5 V.  
1
2
(Short)  
(Open)  
The power supply for PORTVDD is generated on the IE-703079-MC-EM1.  
1
2
3
22  
Users Manual U15447EJ1V0UM  
 
CHAPTER 3 FACTORY SETTINGS  
Item  
Description  
Remark  
JP1  
16 MHz clock supplied for main system clock  
Oscillator mounted  
JP2Note  
Internal clock used for main system clock  
1
2
3
(1-2 Shorted)  
JP3  
Oscillator mounted  
32.768 kHz clock supplied for subsystem clock  
Note Use JP2 with the factory settings.  
23  
User’s Manual U15447EJ1V0UM  
 
CHAPTER 4 CAUTIONS  
4.1 VDD0 and PORTVDD of Target System  
(1) VDD0 in the target system is used to sense the level for target system power supply ON/OFF.  
When VDD0 is lower than 1 V, it is judged that the target system is not connected, and mapping of the target  
memory cannot be performed with a debugger (FCAN cannot be used).  
When VDD0 is 1 V or higher, it is judged that the target system is connected, and mapping of the target  
memory can be performed with a debugger (FCAN can be used).  
(2) PORTVDD in the target system is not supplied directly to the emulator chip; it is connected to the target voltage  
emulation circuit.  
When PORTVDD is lower than 3 V, VCC (5 V) in the internal emulator is supplied to the emulator chip.  
When PORTVDD is 3 V or higher, a voltage of the same potential as PORTVDD in the target system is  
generated and supplied to the emulator chip.  
Figure 4-1. Schematic Diagram of Power Supply Acquisition  
IE-703079-MC-EM1  
IE-703002-MC  
ON/OFF?  
VDD (8 pins)  
V850/SF1  
I/O chip  
Target  
system  
Relay  
Evaluation  
chip  
VCC (5 V)  
PORTVDD  
(66 pins)  
Target voltage  
emulation  
24  
User’s Manual U15447EJ1V0UM  
 
CHAPTER 4 CAUTIONS  
4.2 NMI Signal  
The input signal (NMI signal) from the target system is delayed (tpD = 0.25 ns (TYP.)) because it passes through  
QS3125 (Q switch), and I/O signals (ports 4, 5, 6, 9, 11) pass through QS3384 (Q switch) before it is input to the  
emulator chip.  
In addition, the DC characteristics change. The input voltage becomes VIH = 2.0 V (MIN.), VIL = 0.8 V (MAX.), and  
the input current becomes IIN = 0.5 µA (MAX.).  
Figure 4-2. NMI Signal Flow Path  
IE-703079-MC-EM1  
NMI signal  
NMI pin  
QS3125  
Target  
system  
Emulator chip  
Port signal  
Port pin  
QS3125  
4.3 VPP Signal  
The VPP signal from the target system is left open in the emulator.  
4.4 NMI Signal Mask Function  
When using the P00/NMI pin in the port mode, do not mask the NMI signal.  
25  
Users Manual U15447EJ1V0UM  
 
CHAPTER 4 CAUTIONS  
4.5 Bus Interface Pin  
The operation of the pin for the bus interface differs between the emulator and the target device as follows.  
Table 4-1. Bus Interface Pin Operation List (1/2)  
(a) During break  
Pin Name  
Internal Memory  
External Memory  
Emulation RAM Target System  
Memory Used by  
Emulator  
Internal  
ROM  
Internal RAM  
Internal  
Peripheral I/O  
F
R
W
R
R
W
R
W
R
W
R
W
A16 to A21  
AD0 to AD15  
ASTB  
Hold the last accessed address  
Active  
Active  
Active  
Active  
H
Active  
Active  
Active  
Active  
Active  
Active  
Active  
Maskable  
Maskable  
H or L  
H
Hi-Z  
H
R/W  
H
DSTB  
H
LBEN  
H
Active  
Active  
Maskable  
Maskable  
H or L  
H
UBEN  
WAIT  
H
Invalid  
HLDRQ  
HLDAK  
WRL  
Maskable  
H or L  
H
H
H
Note  
Note  
H
WRH  
H
H
RD  
H
Note  
Note Active  
Caution When accessing an FCAN register with the external memory expanded, a bus cycle for FCAN  
access is generated in AD0 to AD15 and A16 to A21. However, R/W, DSTB, LBEN, UBEN, WRL,  
WRH, and RD are inactive.  
Remarks 1. F:  
Fetch  
R:  
W:  
Read  
Write  
2. H:  
L:  
High-level output  
Low-level output  
Hi-Z: High-impedance  
26  
User’s Manual U15447EJ1V0UM  
 
CHAPTER 4 CAUTIONS  
Table 4-1. Bus Interface Pin Operation List (2/2)  
(b) During run  
Pin  
Internal Memory  
External Memory  
Emulation RAM Target System  
Name  
Internal ROM  
Internal RAM  
Internal  
Peripheral I/O  
F
R
F
R
W
R
W
F
R
W
F
R
W
A16 to  
A21  
Hold the last accessed address  
Active  
Active  
AD0 to  
AD15  
Hi-Z  
Active  
Active  
ASTB  
R/W  
H
Active  
Active  
H
Active  
Active  
Active  
Active  
Active  
Maskable  
Maskable  
H or L  
H
H
DSTB  
LBEN  
UBEN  
WAIT  
HLDRQ  
HLDAK  
WRL  
H
H
Active  
Active  
Maskable  
Maskable  
H or L  
H
H
Invalid  
Maskable  
H or L  
H
H
H
Note  
Note  
H
WRH  
RD  
H
H
H
Note  
Note Active  
Caution When accessing an FCAN register with the external memory expanded, a bus cycle for FCAN  
access is generated in AD0 to AD15 and A16 to A21. However, R/W, DSTB, LBEN, UBEN, WRL,  
WRH, and RD are inactive.  
Remarks 1. F:  
Fetch  
R:  
W:  
Read  
Write  
2. H:  
L:  
High-level output  
Low-level output  
Hi-Z: High-impedance  
27  
User’s Manual U15447EJ1V0UM  
 
CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICE AND TARGET INTERFACE CIRCUIT  
Differences between the signal lines of the target device and the signal lines of the IE-703079-MC-EM1 target  
interface circuit are described in this chapter.  
The target device is a CMOS circuit, whereas the target interface circuit of the IE-703079-MC-EM1 is configured  
with an emulation circuit such as a gate array TTL or CMOS-IC.  
When debugging the IE system connected to the target system, the IE system emulates as if the real target device  
is operating on the target system.  
Small differences occur however, because the IE system is emulating actual operation.  
(1) Signals input/output to/from the emulation CPU µPD70F3079Y  
(2) Other signals  
The IE-703079-MC-EM1 circuit regarding the (1) and (2) signals described above is as follows.  
(1) Signals input/output to/from the emulation CPU µPD70F3079Y  
P00  
P07/INTP6 to P01/INTP0  
P15/SCK1/ASCK0 to P10/SO0/SDA0  
P27 to P20/SI3/RXD1  
P34/VM45/TI71 to P30/TI2/TO2  
P77/ANI7 to P70/ANI0  
P83/ANI11 to P80/ANI8  
P107/KR7/TO1 to P100/KR0/TO7  
(2) Other signals  
NMI  
P47/AD7 to P40/AD0  
P57/AD15 to P50/AD8  
P65/A21 to P60/A16  
P96/HLDRQ to P90/LBEN  
P117/CANRX2 to P110/WAIT  
X1, XT1  
RESET  
CLKOUT  
PORTVDD  
CPUREG  
VPP/MODE  
X2, XT2  
GND0, GND1, GND2, PORTGND  
28  
User’s Manual U15447EJ1V0UM  
 
CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICE AND TARGET INTERFACE CIRCUIT  
Figure 5-1. Equivalent Circuit of Emulation Circuit (1/5)  
Probe side  
IE system side  
IN/OUT  
P00/NMI  
QS3125  
(P00/NMI)  
P01/INTP0  
P02/INTP1  
P03/INTP2  
P04/INTP3  
P05/INTP4/ADTRG  
P06/INTP5  
P07/INTP6  
IN/OUT  
IN/OUT  
P10/SI0/SDA0  
P11/SO0  
P12/SCK0/SCL0  
P13/SI1/RXD0  
P14/SO1/TXD0  
P15/SCK1/ASCK0  
µ
PD70F3079Y  
P20/SI3/RXD1  
P21/SO3/TXD1  
P22/SCK3/ASCK1  
P23/SI4  
IN/OUT  
P24/SO4  
P25/SCK4  
P26  
P27  
P30/TI2/TO2  
P31/TI3/TO3  
P32/TI4/TO4  
P33/TI5/TO5  
P34/VM45/TI71  
IN/OUT  
PD70F3079Y  
µ
IN/OUT  
QS3384  
QS3384  
Connector  
74VHC125  
PD703091R  
µ
(AD7 to AD0)  
P40/AD0  
P41/AD1  
P42/AD2  
P43/AD3  
P44/AD4  
P45/AD5  
P46/AD6  
P47/AD7  
OUT  
(P47 to P40)  
FPGA  
OR2T40A  
IN  
29  
User’s Manual U15447EJ1V0UM  
 
CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICE AND TARGET INTERFACE CIRCUIT  
Figure 5-1. Equivalent Circuit of Emulation Circuit (2/5)  
Probe side  
IE system side  
IN/OUT  
QS3384  
QS3384  
Connector  
74VHC125  
µ
PD703091R  
(AD15 to AD8)  
P50/AD8  
P51/AD9  
P52/AD10  
P53/AD11  
P54/AD12  
P55/AD13  
P56/AD14  
P57/AD15  
OUT  
(P57 to P50)  
FPGA  
OR2T40A  
IN  
OUT  
QS3384  
QS3384  
Connector  
74VHC125  
PD703091R  
µ
(A21 to A16)  
P60/AD16  
P61/AD17  
P62/AD18  
P63/AD19  
P64/AD20  
P65/AD21  
OUT  
(P65 to P60)  
FPGA  
OR2T40A  
IN  
P70/ANI0  
P71/ANI1  
P72/ANI2  
P73/ANI3  
P74/ANI4  
P75/ANI5  
P76/ANI6  
P77/ANI7  
IN  
PD70F3079Y  
µ
P80/ANI8  
P81/ANI9  
P82/ANI10  
P83/ANI11  
IN  
OUT  
µ
QS3384  
QS3384  
Connector  
74VHC125  
PD703091R  
(HLDAC to LBEN)  
P90/LBEN  
P91/UBEN  
P92/R/W  
OUT  
P93/DSTB  
P94/ASTB  
P95/HLDAC  
(P95 to P90)  
FPGA  
OR2T40A  
IN  
30  
Users Manual U15447EJ1V0UM  
 
CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICE AND TARGET INTERFACE CIRCUIT  
Figure 5-1. Equivalent Circuit of Emulation Circuit (3/5)  
Probe side  
IE system side  
IN  
QS3384  
QS3384  
Connector  
74VHC125  
µ
PD703091R  
(HLDRQ)  
OUT  
P96/HLDRQ  
(P96)  
FPGA  
OR2T40A  
IN  
P100/KR0/TO7  
P101/KR1/TI70  
P102/KR2/TI00  
P103/KR3/TI01  
P104/KR4/TO0  
P105/KR5/TI10  
P106/KR6/TI11  
P107/KR7/TO1  
IN/OUT  
µ
PD70F3079Y  
P110/WAIT  
P111  
IN  
P112  
P113  
FPGA  
74VHC125  
74VHC125  
OR2T40A  
OUT  
QS3384  
QS3384  
OUT  
P114/CANTX1  
P116/CANTX2  
FPGA  
OR2T40A  
IN  
OUT  
µ
PD70F3079F  
QS3384  
QS3384  
74VHC125  
OUT  
P115/CANRX1  
P117/CANRX2  
FPGA  
OR2T40A  
IN  
IN  
µ
PD70F3079Y  
31  
Users Manual U15447EJ1V0UM  
 
CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICE AND TARGET INTERFACE CIRCUIT  
Figure 5-1. Equivalent Circuit of Emulation Circuit (4/5)  
Probe side  
IE system side  
X1  
X2  
1-2 shorted  
2 3  
X1  
µ
PD70F3079Y  
1 MΩ  
1
JP2  
7
1
JP1  
XT1  
XT2  
XT1  
PD70F3079Y  
µ
7
1
JP3  
3 V  
5.1 kΩ  
RESET  
Socket  
Socket  
µ
PD703091R  
PD703091R  
CLKOUT  
µ
VCC  
100 Ω  
Relay  
PORTVDD  
Internal circuit  
VCC  
1 MΩ  
µ
100  
F
+
G6H-2F  
VCC  
2.2 kΩ  
+
3.3 kΩ  
µ
PC393  
32  
Users Manual U15447EJ1V0UM  
 
CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICE AND TARGET INTERFACE CIRCUIT  
Figure 5-1. Equivalent Circuit of Emulation Circuit (5/5)  
Probe side  
IE system side  
ADCVDD  
ADCGND  
CPUREG  
VPP/MODE  
X2  
Open  
Open  
Open  
Open  
µ
0.1  
F
3.3 V  
µ
PD70F3079Y  
JP1  
JP3  
XT2  
GND0  
GND1  
GND2  
PORTGND  
33  
Users Manual U15447EJ1V0UM  
 
APPENDIX PACKAGE DRAWINGS  
IE-703002-MC + IE-703079-MC-EM1 (Unit: mm)  
571  
103  
166  
302  
Top view  
Pin 1 direction  
Side view  
IE-703002-MC  
IE-703079-MC-EM1  
Bottom view  
Top view  
33.0  
34  
User’s Manual U15447EJ1V0UM  
 
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